Editor's Preface          [vii]

1. Physical Fault Modeling and Simulation for VLSI MOS Circuits          [1]

Mona E. Zaghloul

2. Designing CMOS Gates to Test Open Faults          [32]

R. Rajsuman

3. Testing Bridging Faults in VLSI          [58]

R. Rajsuman

4. Built-in Self-Test Techniques for Programmable Logic Arrays          [90]

Chun-Yeh Liu and Kewal K. Saluja

5. Value Assignment Implication Constraints and Design for Testability          [123]

Bijan Karimi and Louis G. Johnson

6. Testable Design Synthesis Methods          [162]

Catherine H. Gebotys and Mohamed I. Elmasry

Author Index          [195]

Subject Index          [198]